Design of VLSI Systems



The top-down design methodology is primarily based on automatic (computer-aided) synthesis of the gate-level netlist, using a behavioral or structural HDL description. The synthesized logic is subsequently mapped onto a standard-cell library or an FPGA (Field Programmable Gate Array). The top-down design methodology is well suited for purely digital designs with relatively short turn-around times and moderate area-performance requirements.



Design of VLSI Systems

[VLSI Design
Flow] Back to the main design flow diagram


Ilhan HATIRNAZ 11/10/1998